project
- FPGA Optimization
Automated FPGA Accelerator OptimizationUniversity of California, Los Angeles | 2022.5 - 2022.11Working with Prof. Jason Cong’s group, researching Automated FPGA Accelerator Design. Combined GNN-based Cost Model with an ML/RL-based Design Space Exploration to achieve FPGA Accelerator Design Automation. - FPGA Doodle Dump
Implement A Game Efficiently on the FPGA BoardUniversity of Illinois at Urbana-Champaign | 2021.9 - 2021.12Ported the game "Doodle Dump" to FPGA with SystemVerilog. Consumed only 400KB memory, 0.5w power to achieve a 50hz frame rate, won the Best Design Prize.